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ISSCC spotlight: Using logic to heal transistor variability

Posted on: 05-Feb-2007

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As transistors shrink, microprocessor designers can run into reverse scaling, in which a 45-nm design can operate at lower frequencies than a 65-nm design due to transistor variability in critical circuits. The International Solid State Circuits Conference, which starts Sunday (Feb. 11th) in San Francisco, includes a handful of papers on how to deal with transistor variability.
The subject is important – most experts rate variability as the biggest problem at the 45-nm generation and beyond. And there is an optimistic glint to these innovative ideas about using transistors, which we have plenty of, to help logic stay healthy and fast.
ISSCC features two papers from IBM researchers on variability management circuits. An IBM Austin research team will describe a distributed critical-path timing monitor (CPM) that is included on the IBM-designed Power6 processor, based on a 65-nm silicon-on-insulator (SOI) technology.
The monitor provides feedback on timing margins: it tracks critical-path delay to within three fanout-of-two (FO2) delays, and tracks timing changes greater than one FO2 delay. The CPM provides information on process variation and localized noise, and detects DC Vdd droops greater than 10 milliVolts.
A second IBM paper from the T.J. Watson research center at Yorktown Heights, N.Y. describes an on-chip digital characterization method for detecting random process variations. The 130-nm test chip uses a sense-amplifier-based test circuit which employs digital voltage measurements instead of the conventional analog current measurements. The proposed circuit helps designers create on-chip, built-in-self-test (BIST) schemes for measuring random variation.
There are several papers from Japan-based teams on digital management circuits.
A paper from NEC Electronics describes how yields can increase sharply by employing fine-grained redundant logic. If a critical circuit is defective, operation switches to a redundant block of logic. Also, the NEC paper details the use of defect-prediction flip-flops. All flip-flops are connected via a scan chain, which traces defect points.
A paper from Renesas Technology describes fine-grained monitoring circuits to track power-supply variations. The circuits are placed at 120 locations on a system-on-chip device, including 26 locations on the SoC’s processor core and supporting cache. The circuits detect power supply variations as small as 800 microVolts, and timing changes as small as 100 picoseconds.
Fujitsu researchers developed an on-chip noise sensor, implemented in 90-nm test chip, which does not interfere with a processor’s operations. The sensor uses histogram counters and variable detection windows to measure periodic and single-events in real time.
 
 
 

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