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Intel's teraflops processor points to 3D memory strategy

Posted on: 13-Feb-2007

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Intel’s announcement at ISSCC this week of its teraflops 80-core research-level processor included a research commitment to 3D memory technology that may blossom into much more than R&D. Justin Rattner, an Intel senior fellow, said Intel would make a more detailed presentation of its 3D memory research project in the next few months.
With IBM committed to embedded DRAM for its server chips (see earlier column), Intel appears to be headed in a 3D direction, connecting MPU logic vertically with L3 cache DRAM or SRAM using many thousands of vertical interconnects.
Intel's research-level teraflops chip unveiled at ISSCC currently uses just 5 kilobytes of on-chip data and instruction memory per core. The next step is to vertically link the 80 floating point tiles with SRAM for each processor core. Rattner said the memory array and logic is co-fabricated, using the same mask set. The heat sink is on top of the logic array, with the lower-power memory array on the bottom.
Server processors require very high bandwidth and super-fast cycle times between logic and memory, needs which are best served by vertical copper interconnects through via openings of the two chips. These “through via” connections can provide tens of thousands of interconnections running at an energy-saving 100 MHz or so. The result is tremendous bandwidth (important for video processing), and lower cache miss rates.
The challenges facing 3D memory implementation are many, but Intel has the resources to deal with all of them. Designing the logic so the vertical studs do not interfere is one challenge. Getting the manufacturing infrastructure organized is another. Thermal issues are yet another.
The need for such fast L3 cache is growing. Intel now has 24 megabytes of L3 SRAM on the Itanium "Montecito" processor, and about 8-9 MB for the Pentium series products. Taking that L3 density to multiple gigabytes with 3D-connected fast DRAM would reduce the number of cache misses sharply, following the rule of thumb that a 4X increase in cache density reduces the cache miss rate by 2X.
Can Intel pull off 3D memory? With Intel’s teraflops 80-core as the research vehicle, 3D memory on Intel’s multi-core server and desktop products may follow.
 

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