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EUV program on brink of moving to alpha demonstration tool phase

Posted on: 28-Feb-2007

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The race is on to ready extreme ultraviolet (EUV) lithography systems for the 32-nm half-pitch generation coming in 2012. A major milestone is expected in the next week or two. ASML shipped two alpha demonstration tools (ADTs) to IMEC and the Albany Nanotech center last year. However, the foil trap sub-system to mitigate debris to the source collector module (SoCoMo) needed last-minute modifications.
At the SPIE Advanced Lithography event in San Jose Tuesday (Feb. 27) ASML vice president Noreen Harned said the foil trap to stop tin atoms from damaging the expensive collector mirrors “had trouble” but that a modified foil would be installed at IMEC and Albany as soon as next week.
That will move the 21-year-old EUV development program from the stage of micro-exposure tools (METs) to full-field ADTs, capable of about 10 wafers per hour at numerical apertures of 0.25.
ASML made a “difficult decision” about two years ago when the ADTs were being planned, Harned said. While xenon gas is an easier source material for the EUV radiation, ASML’s scientists decided to use tin for the ADT’s, arguing that the higher conversion efficiency of tin made it the only path toward full production systems. The challenge with tin is mitigation of the high-energy debris which occurs when the tin droplets are hit with a high-energy source.
“We decided that ASML needed to learn to use tin in the source collector module, instead of xenon. We needed to learn how to use tin in terms of debris, power, and source control,” she said at a SPIE session on EUV lithography. That meant developing a tin foil trap, which is now being tested with a dummy collector.     
One way to clock the readiness of EUV is the source power of the EUV radiation. To achieve acceptable throughput, the EUV scanners will need at least 180 Watts of the 13.4-nm EUV radiation. Even that 180-Watt spec depends on finding an EUV resist with excellent sensitivity.
Harned said the ADTs also will provide learning on the EUV-specific wafer handling challenges, which must be done in a vacuum environment. Flare is another challenge: the short EUV wavelengths result in high flare. Nevertheless, ASML has used the ADTs to print clear 32-nm lines and spaces, and contact hole patterns, using the Rohm and Haas MET-2d resist with 40 milliJoules of sensitivity.
At the SPIE EUV session, Stefan Wurm, the EUV program manager at Sematech, said the next goal is to develop EUV source generation systems with 50 Watts of power by 2009, at 90 percent uptime. Those pre-production systems would go into pilot lines to prove out EUV lithography.
Besides source power generation, mask blank defects are another major challenge. The masks are built on multi-coated square blanks, capable of reflecting the EUV light to the wafer surface. Sematech has developed ion beam repair systems which can smooth defects on the expensive substrates. Wurm said the newest repair system is capable of smoothing 21-nm-deep and 100-nm-wide gouges in the mask blank surfaces. The goal is to reduce defects to less than 0.003 defects per square centimeter, for mask blank defects as small as 25 nm, by 2009.

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