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Search for post-CMOS logic identifies early candidates

Posted on: 13-Mar-2007

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By Paola Gargini’s count, there are three or four types of devices that meet the definition of what is needed for post-CMOS logic, which exhibit one or two parameters better than what CMOS can do.
Well before the 2020 time frame, there is early evidence pointing to new devices that show gain, with higher mobility, at lower switching energy, said Gargini, who is Intel’s director of technology strategy.
True, most of these demonstrations have been under low-temperature conditions, and the Nanotechnology Research Institute’s (NRI) requirement is room-temperature operation. Gargini argues that at this point, “we don’t need an implementation, just a demonstration that under some conditions these devices can show high current and voltages, with minimal energy.”
Bob Doering, a Texas Instruments fellow, said electrons have been shown to have spin effects and pseudo-spintronic effects that can be manipulated to form a new computational state variable. Many of these experimental devices rely on detection of minute magnetic fields.
One field of research is quantum point contacts. Another relies on quantum tunneling through different material layers.
Much of the research is being done at the simulation level, and what little experimental evidence is out there has been under low-temperature conditions. While IBM’s Almaden lab and other research centers have been able to use atomic force microscopes to move individual electrons around, the ability to measure an electron’s spin remains an elusive goal.
One can be encouraged, or not, by the current state of understanding of what post-CMOS devices will look like 20 years from now. What is encouraging is the speed in which the semiconductor industry has rallied behind the challenge, led in good measure by Gargini, Doering, NRI director and IBM Almaden researcher Jeff Welser, Mike Rocco, senior adviser for nano-engineering at the National Science Foundation, Jim Hutchby, the director of devices sciences at the SRC, and many others. 
Just a few years ago, the electronics industry was feeling left out of nanotech funding, as most of the federal attention went to biotech. Then Gargini made a proposal to the board of the Semiconductor Industry Association to start the Nanoelectronics Research Initiative. One goal was to establish three centers of excellence by 2008. Funding for the centers would come from several sources, including the six large SIA member companies, from the states where the centers of excellence would be based; and from the semiconductor company dominant in that state.
WIN, the Western Institute of Nanoelectronics, was set up last year with backing from California and Intel.
By the first quarter of 2006, New York and IBM had established INDEX, the Institute for Nanoelectronics Discovery and Exploration. SWAN, the Southwest Acadamy of Nanoelectronics, was announced last September, with funding from Texas Instruments and the state of Texas.
“Everything we wanted to set in place is set up, and we did it by 2006 instead of by 2008,” Gargini said.

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