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Strain techniques to get a boost at Symposium on VLSI Technology

Posted on: 30-Mar-2007

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The paper abstracts for the 2007 Symposium on VLSI Technology, planned for June 12-14 in Kyoto, Japan, point to several ways to further enhance strain in both P- and NFETs.
Many companies are evaluating the cost/performance tradeoffs of adding a dose of embedded carbon to the source and drain regions of the NFETs. To date, Intel and more recently several other companies have sharply increased the mobility of the PFETs by embedding silicon germanium at the source and drain regions, creating a compressive stress, i.e. pushing the lattice inwards. PFETs have benefited from strain engineering more than the NFETs, which gain somewhat from tensile strain induced from nitride capping layers. (see two papers on strain techniques in the paper section of WeSRCH, one by Mark Bohr of Intel and the other by Dick James of ChipWorks.)
At the VLSI symposium, IBM researchers will describe using a novel solid phase epitaxy technique to deposit carbon in the NFET source and drain regions. The IBM process, according to the abstract, “uses no recess etch or epi deposition, adds minimal process cost, and can be easily integrated into a standard CMOS process.”
The added 1.6 percent of substitutional carbon helps create a 615 megaPascal uniaxial tensile stress, which leads to a 35 percent improvement in electron mobility in sub-40-nm MOSFETs.
The National University of Singapore has tested a new transistor structure that creates a strain transfer structure (STS) beneath the channel. The underlying strain layers couple with the source and drain lattice stressors, and with the overlying channel region. The Singapore group created strained NFETs with a SiGe STS and silicon carbon-strained source and drain structure, as well as PFETs with a silicon-carbon STS and SiGe source and drain regions.
Sony engineers will go to Kyoto to present their strain engineering work, using a dummy gate Damascene process, rather than the gate-first process, for PFET devices. The Damascene process supported creation of a channel recess region, and boosted the drive current by 14 percent. Sony may combine the strain techniques with high-k and metal gates in forthcoming low-power and high-performance transistors.
Toshiba engineers modified PFETs by optimizing a recessed SiGe source-drain technology in several different ways, to be described at the Kyoto meeting. The 24-nm gate length devices have drive currents of 714 microAmperes per micron at a 1 V power supply, which Toshiba claims is the best PFET drive current reported to date.
If some of these strain enhancement approaches work out in manufacturing, strain could enhance CMOS performance through the next two or three technology generations at least.
Information about the symposium can be found at:

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About weQuest:
weQuest's are written by G Dan Hutcheson, his career spans more than thirty years, in which he became a well-known as a visionary for helping companies make businesses out of technology. This includes hundreds of successful programs involving product development, positioning, and launch in Semiconductor, Technology, Medicine, Energy, Business, High Tech, Enviorntment, Electronics, healthcare and Business devisions.

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