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Spansion's Eclipse to shake up flash market with 4-bpc operation

Posted on: 03-Apr-2007

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Spansion added excitement to the never-boring flash memory business, announcing today (April 3rd) its Eclipse flash family, which promises to offer four-bit-per-cell (bpc) storage in a programmable flash product by the middle of next year.
Eclipse could reduce the bill of materials (BOM) in high-end feature phones by replacing NOR and NAND memories with a single architecture that is fast enough to execute code and dense enough to store multimedia data.
Spansion will ship 65-nm, 2-bpc Eclipse chips later this year. Things get more interesting next year when 45-nm production begins and Spansion commences 4-bpc production. Then, handset manufacturers can adapt their operating systems to switch the Eclipe chips on the fly, employing 2-bpc operation when transferring code to DRAM and switching to 4-bpc when downloading MP3 music files, for example.
John Nation, a Spansion product manager, said Eclipse’s appeal is that it will allow handset makers to move to a two-chip memory stack, with one fast DRAM chip and another Eclipse flash device.
Can Eclipse do the functions of both NOR and NAND?
Nand architectures have fast write times but suffer from slow initial access, so read times are too slow to execute code. Conventional Nand chips do not have both data and address buses, and so the interface to logic tends to be more complex. Also, Nand tends to require more error correction code.
Rather than the simpler state machines of previous flash products, the Eclipse chips have a programmable controller on board to support ECC, built-in-self-test, and the 2bpc/4-bpc operation. The controller requires no extra mask steps.
Nation argues that Nand products have enjoyed higher densities to date because the Nand vendors have been quicker at moving to the next process nodes, and can switch between Nand and DRAM product lines. “We’ve changed that,” Nation said, by moving from a 110-nm process in 2005 to 90-nm in 2006 to 65-nm in 2007. By next year, Eclipse will made on the SP1 line in Japan at 45-nm design rules.
Top-end smart phones, which use one memory stack for the baseband processor and another for the applications processor, probably will continue to use high-density Nand devices alongside NOR and DRAM. In the mid-range feature phones, Nation said Eclipse could compete at the 512-Mbit to 2 Gbit densities, based on the 65-nm process generation.
With 4-bpc on the horizon, Spansion could find a lucrative target in the high-volume feature phones that offer more than voice but which retain the penny-pinching BOM ways of the low-end voice phones. It may all come down to yields, die sizes, and keeping Eclipse’s stated promise of a lower bill of materials.
What is exciting is that Spansion has taken its earlier promise of 4-bpc and married it with a dense  architecture that supports NOR code execution. Now its up to the NOR and Nand vendors to respond.

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