IBM’s April 12th announcement that it will bring through-silicon vias (TSVs) to commercial products is the first time a company has crossed from R&D to commercial production of 3D TSV chips. Big Blue has thrown down the gauntlet, saying the Z dimension is ready to be exploited -- despite a multitude of engineering challenges.
IBM first step is to vertically connect power amplifier ICs to a ground plane layer, using an interposer layer. The second phase is to connect 45-nm versions of the server-use Power microprocessors to a power distribution layer containing capacitors and voltage regulators.
Lisa Su, vice president of semiconductor research and development, said power distribution is an under-appreciated challenge: “Today most of that is done with fat wires on the last few levels, but that is not enough. These chips are suffering from not enough decoupling capacitance. They are going so fast and the die are relatively large, so as we go to a larger number of cores we get inconsistent power across the chip,” she said.
The Holy Grail is to learn enough about TSVs to implement a processor-to-memory solution, going from hundred of vias per square centimeter on the power amplifiers, to thousands on the Power/power distribution stack, to tens of thousands of TSVs per sq. cm. on a MPU-memory stack.
“We needed to get confidence that this approach would work in a manufacturing environment, and then work up from there. That is still what is necessary going forward, to practice the technology, learning all of the engineering steps, such as etching these very high aspect ratio holes, and aligning them correctly.
“The etching is relatively benign, but we have to ensure that we are not introducing a lot of particles or defects. These are very small dimensions on these chips, and this process must withstand our defect density requirements,” Su said.
Starting with 10-micron vias and working down to 0.2-micron diameters, IBM plans to move year-by-year up the via density curve as its multi-core processors require more bandwidth.
Starting with the Blue Gene processor used in supercomputers, IBM will connect vertically to embedded DRAM slices as a “level 2.5” cache. The Blue Gene chip now being designed holds 95,000,000 transistors and has more than 17,000 3D interconnects.
Also underway is a 65-nm SRAM design optimized with more than 20,000/cm2 of 3D interconnects.
Then IBM will connect its Power processors to SRAMs and embedded DRAMs, increasing the number of chips in the stack and refining the via density.
“The ultimate way to really take advantage of TSVs is to rearchitect the processors in a way that uses different levels of caches, different from traditional processors. That is part of our work we are doing now, so that we can take advantage of all that this is worth. We see this as an enabling technology for massively parallel, multi-core capabilities,” Su said.
About weQuest: weQuest's are written by G Dan Hutcheson, his career spans more than thirty years, in which he became a well-known as a visionary for helping companies make businesses out of technology. This includes hundreds of successful programs involving product development, positioning, and launch in Semiconductor, Technology, Medicine, Energy, Business, High Tech, Enviorntment, Electronics, healthcare and Business devisions.