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IBM brings air gaps to the 32-nm BEOL

Posted on: 03-May-2007

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If IBM’s “plan of record” to introduce vacuum gaps to its interconnect stack at the 32-nm node goes forward, it will bring yet another form of innovation to the industry. Beyond that, it heralds a first introduction of self-assembling materials that can be coaxed into forming patterns and holes at sub-lithographic dimensions.
Air gaps are actually vacuum spaces which better insulate the copper wires, preventing charge from leaking from one wire to an adjacent wire. By creating a honeycomb of vacuum slots within a conventional SiCOH dielectric material, the effective dielectric constant can be reduced to 2.0, compared with about 3.0 for the 65-nm process and 2.4 for IBM’s ultra-low-k (ULK) SiCOH material used at critical levels of the 45-nm node, said Dan Edelstein, an IBM fellow who leads the company’s back end of the line (BEOL) technology strategy.
While the process involves sacrificial materials, the end result is a chip with no new materials remaining. Also, conventional tooling is used to create the vacuum gaps.
“These are spin and bake-on treatments, using a standard tube furnace,” Edelstein said at a briefing in San Francisco on Tuesday, May 1st.
Other companies have developed vacuum gaps by introducing new materials to the interconnect stack. None of these approaches have resulted in commercially manufacturable solutions. The IBM approach results in gaps which are hermetically sealed, with existing materials. Tantalum acts as a natural getterer, ensuring that no moisture remains in the dielectric.
IBM tested the approach by fabricating an existing 65-nm processor with the airgap dielectric, and reduced the interconnect capacitance by about 35 percent. At the chip level, performance increased by about 10 percent, while active power consumption was reduced by about 15 percent.
The IBM work is not an R&D exercise: at the San Francisco briefing, the company demonstrated a server with a 65-nm processor using the airgap dielectrics.
At 20 nanometers, the gaps are one-half the minimum spacing of the lithographically designed lines and spaces. “With air gaps, we are just breaking the ice” in the use of self assembling materials, Edelstein said.
John E. Kelly III, a senior vice president at IBM, said “this is the first time the industry has used self-assembling nanotechnology. The industry has used atomic level deposition, but it has never leveraged self-assembling materials to form patterns at sub-lithographic dimensions.”
IBM uses one form of the self-assembling process for the critical 1X wiring levels, while a lithographic process is used for the intermediate levels.
For the 1X levels, a transfer layer and hard mask are deposited, followed by a deposition and cure of the proprietary diblock copolymer materials. The diblock copolymers form regular patterns of holes in a phase separation process.
Then, nano-holes are etched into the hardmask, and a lithographically defined block-out pattern is created. The pattern is created in the transfer layer, and etched into the SiCOH dielectric.
These damaged areas of SiCOH dielectric are treated with acid to create contiguous gaps, or nano-holes. Finally, a second capping layer is deposited and the gaps in the dielectric are sealed in a vacuum chamber.
“What we are doing is inviting damage (to the dielectric). Then we dip it in acid to dissolve the damaged areas,” said Edelstein, who was the lead engineer 10 years ago when IBM incorporated copper interconnects into its BEOL.
 
 

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