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IBM's Edelstein: airgap reliability "looks good"

Posted on: 04-May-2007

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IBM’s airgap interconnect technology, announced Thursday, gave appropriate credit to IBM fellow Dan Edelstein, to the IBM Almaden and Watson research laboratories, and the Albany Nanotech research facility. Edelstein last appeared on the world stage at the 1997 International Electron Devices Meeting in Washington, D.C., where he announced IBM’s switch from aluminum to copper wiring.
Air gap, which has been "under the radar for the past three years," provides a nice bookend to copper, said Edelstein, the BEOL technology strategy manager at IBM.
The key question facing vacuum gaps is reliability. Asked about that, Edelstein said “every measure looks good. I worry less about reliability at this point than I do about yields.”
Gary Patton, an IBM vice president of technology development, said the initial reliability tests are positive enough to make airgap technology “the plan of record” for 2009 at the 32-nm technology generation.
At the San Francisco briefing, it became clear that airgap is not a niche technology that will only be applied to high-end server processors. As part of the 32-nm Fishkill-developed SOI process, airgap technology also is available to AMD, Freescale, Sony, and Toshiba, the current partners in the high-performance SOI process.  
At the 32-nm node, both AMD and probably Freescale are likely to use a process identical to IBM’s. Thus far, Sony and Toshiba have been more independent, taking process technologies  developed at Fishkill and incorporating them into their own process flows.
Because IBM tends to use the same BEOL for its SOI process and its bulk CMOS process, the airgap approach could be across-the-board at the 32-nm node, Patton said. In that case, it also would be available to Samsung, Chartered, and Freescale.
One or more new companies are expected to join the Fishkill alliance soon, IBM managers indicated at the briefing. (Freescale belongs to both the SOI and bulk alliances, while Chartered licenses the SOI process for manufacturing at its Fab 7 in Singapore.)
Edelstein showed extensive test data. Also, an IBM server, which IBM said was based on a 65-nm processor with air-gapped wiring levels, was running in the back of the venue at San Francisco.
Edelstein noted that shrinks mean transistors get faster but interconnects get slower, as resistance increases for thinner wires. Besides airgap, there aren’t many options. Copper is unlikely to be replaced by carbon nanotubes in the interconnect stack, he said. Also, silver-copper alloy wires don’t improve the situation.
What does airgap technology bring to the table?
Capacitance modeling shows that airgap reduces wiring capacitance by as much as 40 percent. The CPU-tuned performance estimates indicate a 10 percent improve in Fmax and a 15 percent reduction in power consumption, Edelstein said during his presentation to analysts.
If immersion and double patterning enable 32-nm-generation patterning, and if high-k can be improved with a more aggressive EOT (effective oxide thickness), then airgap help improve interconnect performance, particularly at the critical 1X aspect ratio levels.
As Patton said, the main challenge is to get high-k and metal gates, immersion and double patterning, air gaps, SOI and strained silicon, to all work together in a complementary way, at high yields and reliability.
If that works out for the 32-nm node, the Fishkill alliance partners will be glad they joined together with the likes of Dan Edelstein.
 
 
 
 
 
 
 
 
 
 
 

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